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1997, 2000 data sheet description the m pd178f098 is a flash memory model of the m pd178076, 178078, 178096, and 178098, and is provided with a flash memory to/from which data can be written/erased with the microcontroller mounted on a printed circuit board. for the detailed functional description, refer to the following users manuals: m pd178078, 178098 subseries users manual: u12790e 78k/0 series users manual - instruction : u12326e features ? serial interface (uart mode) ? iebus tm controller ? pin-compatible with mask rom models (except v pp pin) ? flash memory: 60k bytes note ? internal high-speed ram: 1024 bytes ? internal extension ram: 2048 bytes note ? buffer ram: 32 bytes ? operable at same supply voltage as mask rom models (v dd = 4.5 to 5.5 v during pll operation) note the capacities of the flash memory and internal extension ram can be changed using the memory size select register (ims) and internal extension ram size select register (ixs). remark for the differences between the flash memory model and mask rom models, refer to 1. differences between m pd178f098 and mask rom models . the electrical specifications (such as supply current) in the m pd178f098 differ from those of the mask rom models. confirm these differences before mass-producing any application set. application field car stereos ordering information part number package m pd178f098gf-3ba 100-pin plastic qfp (14 20) mos integrated circuit m pd178f098 document no. u12920ej1v0ds00 date published june 2000 n cp(k) printed in japan 8-bit single-chip microcontroller the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd178f098 2 data sheet u12920ej1v0ds00 development of 8-bit dts series models under mass production models under development 100 pins 100 pins 100 pins internal iebus controller internal iebus controller and uart internal uart pd178098 subseries m pd178078 subseries m pd178048 subseries m m m m m 80 pins 80 pins internal osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel pd178f048 m pd178f098 m pd178f134 m pd178f124 m pd178p018a m 80 pins 80 pins internal lcd and uart internal lcd and uart pd178034 subseries internal osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel 80 pins 80 pins internal uart internal uart pd178024 subseries 80 pins 80 pins 80 pins limits functions of pd178018a subseries m pd178018a subseries pd178003 subseries flash memory model or prom model mask rom model
3 data sheet u12920ej1v0ds00 m pd178f098 (1/2) item functions internal flash memory 60k bytes memory high-speed ram 1024 bytes buffer ram 32 bytes extension ram 2048 bytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution ? 0.32 m s/0.64 m s/1.27 m s/2.54 m s/5.08 m s (with crystal resonator of f x = 6.3 mhz) time ? 0.44 m s/0.89 m s/1.78 m s/3.56 m s/7.11 m s (with crystal resonator of f x = 4.5 mhz) note 1 instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits 8 bits) ? bit manipulation (set, reset, test boolean operation) ? bcd adjustment, etc. i/o port total : 80 pins ? cmos input : 8 pins ? cmos i/o : 64 pins ? n-ch open-drain output : 8 pins a/d converter 8-bit resolution 8 channels serial interface ? 3-wire/sbi/2-wire/i 2 c bus note 2 mode selectable : 1 channel ? 3-wire mode : 1 channel ? 3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1 channel ? uart mode : 1 channel iebus controller provided timer ? basic timer (timer carry ff (10 hz)) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel buzzer output beep0 pin: 1 khz, 1.5 khz, 3 khz, 4 khz buz pin: 0.77 khz, 1.54 khz, 3.08 khz, 6.15 khz (with crystal resonator of f x = 6.3 mhz) vectored maskable internal : 15, external: 8 interrupt non-maskable internal: 1 source software 1 pll division mode 2 types frequency ? direct division mode (vcol pin) synthesizer ? pulse swallow mode (vcol and vcoh pins) reference seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 khz) frequency charge pump error out output: 2 pins phase unlock detectable in software comparator functional outline notes 1. when using the iebus controller, the 4.5-mhz crystal resonator cannot be used. use the 6.3-mhz crystal resonator. 2. when the i 2 c bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult nec when ordering a mask.
m pd178f098 4 data sheet u12920ej1v0ds00 (2/2) item functions frequency counter frequency measurement ? amifc pin: for 450-khz counting ? fmifc pin: for 450-khz/10.7-mhz counting standby function ? halt mode ? stop mode reset ? reset by reset pin ? internal reset by watchdog timer ? reset by power-on clear circuit ? detection of less than 4.5 v note (reset does not occur, however.) ? detection of less than 3.5 v note (during cpu operation) ? detection of less than 2.3 v note (in stop mode) supply voltage ? v dd = 4.5 to 5.5 v (during cpu, pll operation) ?v dd = 3.5 to 5.5 v (during cpu operation) package 100-pin plastic qfp (14 20) note these voltages are the maximum values. in practice, the chip may be reset at voltages lower than these.
5 data sheet u12920ej1v0ds00 m pd178f098 pin configuration (top view) ? 100-pin plastic qfp (14 20) m pd178f098gf-3ba 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p06/intp6 p05/intp5 p04/intp4 p124 p123 p122 p121/rx0 p120/tx0 p77 p76 p75/txd0 p74/rxd0 p137 p136 p135 p134 p133 p132 p131/to51 p130/to50 p37/buz p36/beep0 p35/ti51 p34/ti50 p33/ti01 p32/ti00 p31/to0 p30/vm45 p03/intp3 p02/intp2 p00/intp0 p01/intp1 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p70/si3 p71/so3 p72/sck3 p73 p50 p51 p52 p53 p54 p55 p56 p57 p10/ani0 p11/ani1 p12/ani2 p13/ani3 av dd p14/ani4 p15/ani5 p16/ani6 gndport v dd port p47 p46 p45 p44 p43 p42 p41 p40 p67 p66 p65 p64 p63 p62 p61 p60 gnd1 p07/intp7 p17/ani7 av ss regcpu v dd regosc x2 x1 gnd0 p100 gnd2 p101/amifc p102/fmifc v dd pll vcoh vcol gndpll eo0 eo1 v pp reset cautions 1. directly connect the v pp pin to gnd0, gnd1, or gnd2 in normal operating mode. 2. keep the voltage at av dd , v dd port, and v dd pll same as that at the v dd pin. 3. keep the voltage at av ss , gndport, and gndpll same as that at gnd0, gnd1, or gnd2. 4. connect each of the regosc and regcpu pins to gnd via a 0.1- m f capacitor.
m pd178f098 6 data sheet u12920ej1v0ds00 pin name amifc : am intermediate frequency counter input ani0-ani7 : a/d converter input av dd : a/d converter power supply av ss : a/d converter ground busy : busy output beep0, buz : buzzer output eo0, eo1 : error out output fmifc : fm intermediate frequency counter input gndpll : pll ground gnd0-gnd2 : ground intp0-intp7 : interrupt input p00-p07 : port 0 p10-p17 : port 1 p20-p27 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5 p60-p67 : port 6 p70-p77 : port 7 p100-p102 : port 10 p120-p124 : port 12 p130-p137 : port 13 regcpu : regulator for cpu power supply regosc : regulator for oscillation circuit reset : reset input rxd0 : uart0 serial data input rx0 : iebus serial data input sb0, sb1 : serial data bus input/output sck0, sck1, sck3 : serial clock input/output scl : serial clock input/output sda0, sda1 : serial data input/output si0, si1, si3 : serial data input so0, so1, so3 : serial data output stb : strobe output ti00, ti01 : 16-bit timer capture trigger input ti50, ti51 : 8-bit timer clock input to0 : 16-bit timer output to50, to51 : 8-bit timer output txd0 : uart0 serial data output tx0 : iebus serial data output vcol, vcoh : local oscillation input v dd port : port power supply v dd pll : pll power supply v dd : power supply vm45 : v dd = 4.5 v monitor output v pp : programming power supply x1, x2 : crystal resonator
7 data sheet u12920ej1v0ds00 m pd178f098 block diagram 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer basic timer serial interface 0 serial interface 1 iebus0 interrupt control buzzer output system control 78k/0 cpu core flash memory (60k bytes) 8 8 8 8 8 8 8 8 8 3 5 8 8 p00-p07 a/d converter ani0/p10- ani7/p17 frequency counter pll voltage regulator pll voltage regulator ti00/p32 ti01/p33 to0/p31 ti50/p34 to50/p130 ti51/p35 to51/p131 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 serial interface 3 si3/p70 so3/p71 sck3/p72 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral vm45/p30 regosc regcpu gnd0 v osc v cpu rx0/p121 tx0/p120 uart0 rxd0/p74 txd0/p75 intp0/p00- intp7/p07 beep0/p36 buz/p37 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port10 port 12 port 13 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 p70-p77 p100-p102 p120-p124 p130-p137 amifc/p101 fmifc/p102 eo0 eo1 vcol vcoh v dd pll gndpll av dd av ss ic gnd2 gnd1 ram (3k bytes)
m pd178f098 8 data sheet u12920ej1v0ds00 contents 1. differences between m pd178f098 and mask rom models ..................................... 9 2. pin function list .......................................................................................................... ............ 10 2.1 port pins ................................................................................................................... ............... 10 2.2 pins other than port pins ................................................................................................... ... 11 2.3 i/o circuits of pins and recommended connections of unused pins ............................. 13 3. memory size select register (ims) ................................................................................. 17 4. internal extension ram size select register (ixs) .............................................. 18 5. interrupt function .......................................................................................................... ....... 19 6. flash memory programming .............................................................................................. 23 6.1 selecting communication mode ........................................................................................... 23 6.2 flash memory programming function ................................................................................. 24 6.3 connecting flashpro iii ..................................................................................................... ..... 25 7. electrical specifications ................................................................................................... 26 8. package drawing ............................................................................................................. ........ 44 9. recommended soldering conditions ............................................................................. 45 appendix a. development tools ............................................................................................... 4 6 appendix b. related documents .............................................................................................. 48
9 data sheet u12920ej1v0ds00 m pd178f098 1. differences between m pd178f098 and mask rom models the m pd178f098 is provided with a flash memory to/from which data can be written/erased with the device mounted on a printed circuit board. the differences between the flash memory model ( m pd178f098) and mask rom models ( m pd178076, 178078, 178096, and 178098) are shown in table 1-1. table 1-1. differences between m pd178f098 and mask rom models item m pd178f098 m pd178076, 178078 m pd178096, 178098 internal memory rom structure flash memory mask rom rom capacity 60k bytes m pd178076: 48k bytes m pd178096: 48k bytes m pd178078: 60k bytes m pd178098: 60k bytes external 2048 bytes m pd178076: 1024 bytes m pd178096: 1024 bytes extension ram m pd178078: 2048 bytes m pd178098: 2048 bytes internal rom capacity selected by equivalent to mask rom m pd178076: cch m pd178096: cch memory size select register (ims) model m pd178078: cfh m pd178098: cfh internal extension ram capacity equivalent to mask rom m pd178076: 0ah m pd178096: 0ah selected by internal extension ram model m pd178078: 08h m pd178098: 08h size select register (ixs) serial interface 4 channels 3 channels ? 3-wire/sbi/2-wire/i 2 c bus mode selectable ? 3-wire/sbi/2-wire/i 2 c bus ? 3-wire (with automatic transmit/receive function) mode selectable ? 3-wire ? 3-wire (with automatic ? uart transmit/receive function) ? 3-wire iebus controller provided not provided provided interrupt source 24 22 21 ic pin not provided provided v pp pin provided not provided electrical specifications and see the relevant data sheet recommended soldering conditions caution the noise resistance and noise radiation differ between flash memory versions and mask rom versions. when considering the replacement of flash memory versions with mask rom versions in the process from trial manufacturing to mass production, adequate evaluation should be carried out using cs products (not es products) of mask rom versions.
m pd178f098 10 data sheet u12920ej1v0ds00 pin name i/o function at reset shared by: p00-p07 i/o port 0. input intp0-intp7 8-bit i/o port. can be set in input or output mode in 1-bit units. p10-p17 input port 1. input ani0-ani7 8-bit input port. p20 i/o port 2. input si1 p21 8-bit i/o port. so1 p22 can be set in input or output mode in 1-bit units. sck1 p23 stb p24 busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 i/o port 3. input vm45 p31 8-bit i/o port. to0 p32 can be set in input or output mode in 1-bit units. ti00 p33 ti01 p34 ti50 p35 ti51 p36 beep0 p37 buz p40-47 i/o port 4. input C 8-bit i/o port. can be set in input or output mode in 1-bit units. p50-p57 i/o port 5. input C 8-bit i/o port. can be set in input or output mode in 1-bit units. p60-p67 i/o port 6. input C 8-bit i/o port. can be set in input or output mode in 1-bit units. p70 i/o port 7. input si3 p71 8-bit i/o port. so3 p72 can be set in input or output mode in 1-bit units. sck3 p73 C p74 rxd0 p75 txd0 p76, p77 C 2. pin function list 2.1 port pins (1/2)
11 data sheet u12920ej1v0ds00 m pd178f098 pin name i/o function at reset shared by: p100 i/o port 10. input C p101 3-bit i/o port. amifc p102 can be set in input or output mode in 1-bit units. fmifc p120 i/o port 12. input tx0 p121 5-bit i/o port. rx0 p122-p124 can be set in input or output mode in 1-bit units. C p130 output port 13. low-level to50 p131 8-bit output port. output to51 p132-p137 n-ch open-drain output port (15 v withstand) C pin name i/o function at reset shared by: intp0-intp7 input external maskable interrupt input whose valid edge input p00-p07 (rising edge, falling edge, or both rising and falling edges) can be specified. si0 input serial data input to serial interface. input p25/sb0/sda0 si1 p20 si3 p70 so0 output serial data output from serial interface. input p26/sb1/sda1 so1 p21 so3 p71 sb0 i/o serial data input/output to/from n-ch open drain i/o input p25/si0/sda0 sb1 serial interface. p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 i/o serial clock input/output to/from serial interface. input p27/scl sck1 p22 sck3 p72 scl n-ch open drain i/o p27/sck0 stb output strobe output for serial interface automatic transmission/ input p23 reception. busy input busy input for serial interface automatic transmission/ input p24 reception. vw45 output v dd = 4.5 v monitor output input p30 ti00 input external count clock input to 16-bit timer (tm0). input p32 ti01 p33 ti50 input external count clock input to 8-bit timer (tm50). input p34 ti51 external count clock input to 8-bit timer (tm51). p35 to0 output 16-bit timer (tm0) output. input p31 to50 8-bit timer (tm50) output. low-level p130 to51 8-bit timer (tm51) output. output p131 beep0 output buzzer output. input p36 buz p37 2.1 port pins (2/2) 2.2 pins other than port pins (1/2)
m pd178f098 12 data sheet u12920ej1v0ds00 pin name i/o function at reset shared by: ani0-ani7 input analog input to a/d converter. input p10-p17 eo0, eo1 output error out output from charge pump of pll frequency C C synthesizer. vcol input inputs local oscillation frequency of pll (in hf and mf C C modes). vcoh input inputs local oscillation frequency of pll (in vhf mode). C C amifc input input to am intermediate frequency counter. input p101 fmifc input input to fm intermediate frequency or am intermediate input p102 frequency counter. rxd0 input serial data input to asynchronous serial interface (uart0). input p74 txd0 output serial data output from asynchronous serial interface input p75 (uart0). tx0 output iebus controller data output. input p120 rx0 input iebus controller data input. input p121 reset input system reset input. C C x1 input connection of crystal resonator for system clock oscillation. C C x2 C CC regosc C regulator for oscillation circuit. connect this pin to gnd via C C 0.1- m f capacitor. regcpu C regulator for cpu power supply. connect this pin to gnd C C via 0.1- m f capacitor. v dd C positive power supply. C C gnd0-gnd2 C ground. C C v dd port C port power supply. C C gndport C port ground. C C av dd C a/d converter positive power supply. keep voltage at this C C pin same as that at v dd 0. av ss C a/d converter ground. keep voltage at this pin same as C C that at gnd0 through gnd2. v dd pll note C pll positive power supply. C C gndpll note C pll ground. C C v pp C pin to apply high voltage at program writing/verifying. C C directly connect this pin to gnd0, gnd1, or gnd2 in normal operating mode. note connect a capacitor of about 1000 pf between the v dd pll and gndpll pins. 2.2 pins other than port pins (2/2)
13 data sheet u12920ej1v0ds00 m pd178f098 2.3 i/o circuits of pins and recommended connections of unused pins table 2-1 shows the types of the i/o circuits of the respective pins and the recommended connections of the pins when they are not used. for the configuration of the i/o circuit of each pin, refer to figure 2-1. table 2-1. i/o circuit type of each pin (1/2) pin name i/o circuit type i/o recommended connection of unused pin p00/intp0-p07/intp7 8 i/o input: connect each of them to v dd , v dd port, gnd0 to gnd2, or gndport via resistor. output: leave open. p10/ani0-p17/ani7 25 input connect these pins to v dd , v dd port, gnd0 to gnd2 or gndport. p20/si1 5-k i/o input: connect each of them to v dd , v dd port, gnd0 to p21/so1 5 gnd2, or gndport via resistor. p22/sck1 5-k output: leave open. p23/stb 5 p24/busy 5-k p25/si0/sb0/sda0 10-d p26/so0/sb1/sda1 p27/sck0/scl p30/vm45 5 p31/to0 p32/ti00 5-k p33/ti01 p34/ti50 p35/ti51 p36/beep0 5 p37/buz p40-p47 p50-p57 p60-p67 p70/si3 5-k p71/so3 5 p72/sck3 5-k p73 5 p74/rxd0 5-k p75/txd0 5 p76, p77 p100 p101/amifc p102/fmifc p120/tx0 p121/rx0 5-k p122-p124 5
m pd178f098 14 data sheet u12920ej1v0ds00 table 2-1. i/o circuit type of each pin (2/2) pin name i/o circuit type i/o recommended connection of unused pin p130/to50 19 output open these pins. p131/to51 p132-p137 eo0 dts-eo1 eo1 vcol, vcoh dts-amp2 input disable pll in software and select pull-down. regosc, regcpu C C connect these pins to gnd0, gnd1, or gnd2 via 0.1- m f capacitor. reset 2 input C av dd C C connect this pin to v dd or v dd port. av ss directly connect these pins to gnd0 to gnd2, or gndport. v pp
15 data sheet u12920ej1v0ds00 m pd178f098 figure 2-1. i/o circuits of respective pins (1/2) remark v dd and gnd are the positive power supply and ground pins for all port pins. take v dd and gnd as v dd port and gndport. type 5-k data output disable p-ch in/out v dd n-ch type 5 type 2 data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable type 8 data output disable p-ch in/out v dd n-ch input enable open drain type 10-d in schmitt trigger input with hysteresis characteristics type 19 out n-ch
m pd178f098 16 data sheet u12920ej1v0ds00 figure 2-1. i/o circuits of respective pins (2/2) note this switch is selectable in software only for the vcol and vcoh pins. remark v dd and gnd are the positive power supply and ground pins for all port pins. take v dd and gnd as v dd port and gndport. type 25 input enable comparator + n-ch p-ch in v ref (threshold voltage) in type dts-amp type dts-eo1 v dd pll gndpll dw up p-ch out v dd pll gndpll n-ch note
17 data sheet u12920ej1v0ds00 m pd178f098 3. memory size select register (ims) the internal memory capacity of the m pd178f098 can be changed using the memory size select register (ims). by using this register, the memory of the m pd178f098 can be mapped in the same manner as a mask rom model with a different internal memory capacity. use an 8-bit memory manipulation instruction to set the ims. this register is set to cfh at reset. figure 3-1. format of memory size select register (ims) ram2 ram1 ram0 selects internal high-speed ram capacity 1 1 0 1024 bytes others setting prohibited ram3 ram2 ram1 ram0 selects internal rom capacity 1 1 0 0 48k bytes 1 1 1 1 60k bytes others setting prohibited table 3-1 shows the setting of ims to perform the same memory mapping as that of a mask rom model. table 3-1. setting of memory size select register targeted model setting of ims m pd178076, 178096 cch m pd178078, 178098 cfh 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims at reset cfh r/w r/w address fff0h
m pd178f098 18 data sheet u12920ej1v0ds00 4. internal extension ram size select register (ixs) the internal extention ram capacity of the m pd178f098 can be changed using the internal extention ram size select register (ixs). by using this register, the memory of the m pd178f098 can be mapped in the same manner as a mask rom model with a different internal extention ram capacity. use an 8-bit memory manipulation instruction to set the ixs. this register is set to 0ch at reset. figure 4-1. format of internal extension ram size select register (ixs) ixram4 ixram3 ixram2 ixram1 ixram0 selects internal extension ram capacity 0 1 0 0 0 2048 bytes 0 1 0 1 0 1024 bytes others setting prohibited table 4-1 shows the setting of ixs to perform the same memory mapping as that of a mask rom model. table 4-1. setting of internal ram size select register targeted model setting of ixs m pd178076, 178096 0ah m pd178078, 178098 08h 7 0 6 0 5 0 4 ixram4 3 i xram3 2 i xram2 1 i xram1 0 i xram0 symbol ixs at reset 0ch r/w r/w address fff4h
19 data sheet u12920ej1v0ds00 m pd178f098 5. interrupt function the m pd178f098 has the following three types and 24 sources of interrupts: ? non-maskable : 1 note ? maskable : 23 note ? software : 1 note two types of watchdog interrupt sources (intwdt), non-maskable and maskable, are available, and either of them can be selected. table 5-1. interrupt sources (1/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration address type note 2 non-maskable C intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intp7 0014h 9 intcsi0 end of transfer by serial interface 0 internal 0016h (b) 10 intcsi1 end of transfer by serial interface 1 0018h 11 intcsi3 end of transfer by serial interface 3 001ah 12 inttm50 generation of coincidence signal of 8-bit 001ch timer/event counter 50 13 inttm51 generation of coincidence signal of 8-bit 001eh timer/event counter 51 14 intser0 reception error of serial interface uart0 0020h 15 intsr0 end of reception by serial interface uart0 0022h 16 intst0 end of transmission by serial interface uart0 0024h 17 intbtm0 generation of coincidence signal of basic 0026h timer notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. the default priority 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type corresponds to (a) to (e) in figure 5-1. name trigger
m pd178f098 20 data sheet u12920ej1v0ds00 table 5-1. interrupt sources (2/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration address type note 2 maskable 18 inttm00 generation of signal indicating coincidence internal 0028h (b) between 16-bit timer counter (tm0) and capture/compare register (cr00) (when cr00 is used as compare register) detection of input edge of ti00/p32 pin external (d) (when cr00 is used as capture register) 19 inttm01 generation of signal indicating coincidence internal 002ah (b) between 16-bit timer counter (tm0) and capture/compare register (cr01) (when cr01 is used as compare register) detection of input edge of ti01/p33 pin external (d) (when cr01 is used as capture register) 20 intie1 iebus0 data access request internal 002ch (b) 21 intie2 iebus0 communication error and start/end 002eh of communication 22 intad end of conversion by a/d converter ad1 0030h (b) software C brk execution of brk instruction C 003eh (e) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. the default priority 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type corresponds to (a) to (e) in figure 5-1. name trigger
21 data sheet u12920ej1v0ds00 m pd178f098 figure 5-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 through intp7) interrupt request priority control circuit vector table address generation circuit standby release signal internal bus interrupt request if mk ie pr isp standby release si g nal priority control circuit vector table address generation circuit internal bus if mk ie pr isp external interrupt rising/falling edge enable registers (egp, egn) interrupt request standby release si g nal priority control circuit vector table address generation circuit internal bus edge detection circuit
m pd178f098 22 data sheet u12920ej1v0ds00 figure 5-1. basic configuration of interrupt function (2/2) (d) external maskable interrupts (inttm00, inttm01) (e) software interrupt remark if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag isp ie if mk prescaler mode register (prm0) pr interrupt request standby release signal priority control circuit vector table address generation circuit internal bus edge detection circuit interrupt request priority control circuit vector table address generation circuit internal bus
23 data sheet u12920ej1v0ds00 m pd178f098 6. flash memory programming the program memory provided in the m pd178f098 is flash memory. the flash memory can be written on-board, i.e., with the m pd178f098 mounted on the target system. to do so, connect a dedicated flash writer (flashpro iii (part number fl-pr3, pg-fp3)) to the host machine and target system. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 6.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 6-1. to select a communication mode, the format shown in figure 6-1 is used. each communication mode is selected depending on the number of v pp pulses shown in table 6-1. table 6-1. communication modes communication mode number of channels pins used number of v pp pulses 3-wire serial i/o (sio3) 1 si3/p70 0 so3/p71 sck3/p72 uart0 1 rxd0/p74 8 txd0/p75 caution be sure to select a communication mode by the number of v pp pulses shown in table 6-1. figure 6-1. communication mode selection format 10 v gnd v dd v pp reset v dd gnd flash memory writing mode v pp pulse
m pd178f098 24 data sheet u12920ej1v0ds00 6.2 flash memory programming function an operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. the major flash memory programming functions are listed in table 6-2. table 6-2. major flash memory programming functions function description batch erase erases all memory contents. batch blank check checks erased status of entire memory. data write writes data to flash memory starting from write start address and based on number of data (bytes) to be written). batch verify compares all contents of memory with input data.
25 data sheet u12920ej1v0ds00 m pd178f098 6.3 connecting flashpro iii connection with flashpro iii differs depending on the communication mode (3-wire serial i/o or uart0). figures 6-2 and 6-3 show the connection in the respective modes. figure 6-2. connection of flashpro iii in 3-wire serial i/o mode flashpro iii pd178f098 m v pp v dd reset clk sck so si gnd v pp v dd reset x1 sck3 si3 so3 gnd figure 6-3. connection of flashpro iii in uart0 mode flashpro iii pd178f098 m v pp v dd reset clk so si gnd v pp v dd reset x1 rxd0 txd0 gnd
26 data sheet u12920ej1v0ds00 m pd178f098 parameter symbol conditions rating unit supply voltage v dd C0.3 to +6.0 v v dd port C0.3 to v dd + 0.3 note 1 v av dd C0.3 to v dd + 0.3 note 1 v v dd pll C0.3 to v dd + 0.3 note 1 v v pp C0.3 to +10.5 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o excluding p130 to p137 C0.3 to v dd + 0.3 v output breakdown v bds p130-p137 n-ch open drain 16 v voltage analog input voltage v an p10-p17 analog input pin C0.3 to v dd + 0.3 v high-level output i oh 1 pin C8 ma current total of p00-p01, p20-p27, p50-p57, and p70-p73 C15 ma total of p02-p07, p30-p37, p40-p47, p60-p67, C15 ma p74-p77, and p120-p124 total of p100-p102 C10 ma low-level output i ol note 2 1 pin peak value 16 ma current r.m.s 8 ma total of p00-p01, p20-p27, p50-p57, peak value 30 ma and p70-p73 r.m.s 15 ma total of p02-p07, p30-p37, p40-p47, peak value 30 ma p60-p67, p74-p77, p120-p124, and r.m.s 15 ma p130-p137 total of p100-102 peak value 20 ma r.m.s 10 ma operating temperature t a during normal operation C40 to +85 c during flash memory programming 10 to 40 c storage temperature t stg C55 to +125 c 7. electrical specifications absolute maximum ratings (t a = 25 c) notes 1. keep the voltage at v dd port, av dd , and v dd pll same as that at the v dd pin. 2. calculate the r.m.s as follows: [r.m.s] = [peak value] x duty caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. be sure to use the product with these ratings never being exceeded. remark unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
27 data sheet u12920ej1v0ds00 m pd178f098 recommended supply voltage ranges (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu is operating and pll is stopped 3.5 5.0 5.5 v data retention voltage v ddr when crystal oscillation stops 2.3 5.5 v output breakdown v bds p130-p137 (n-ch open drain) 15 v voltage dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit high-level input v ih1 p10-p17, p21, p23, p30, p31, p36, p37, p40-p47, 0.7 v dd v dd v voltage p50-p57, p60-p67, p71, p73, p75-p77, p100-p102, p120, p122-p124 v ih2 p00-p07, p20, p22, p24-p27, p32-p35, p70, p72, 0.8 v dd v dd v p74, p121, reset low-level input v il1 p10-p17, p21, p23, p30, p31, p36, p37, p40-p47, 0 0.3 v dd v voltage p50-p57, p60-p67, p71, p73, p75-p77, p100-p102, p120, p122-p124 v il2 p00-p07, p20, p22, p24-p27, p32-p35, p70, p72, 0 0.2 v dd v p74, p121, reset high-level output v oh1 p00-p07, p20-p24, p30-p37, 4.5 v v dd 5.5 v, v dd C 1.0 v voltage p40-p47, p50-p57, p60-p67, i oh = C1 ma p70-p77, p100-p102, 3.5 v v dd < 4.5 v, v dd C 0.5 v p120-p124 i oh = C100 m a v oh2 eo0, eo1 v dd = 4.5 to 5.5 v, v dd C 1.0 v i oh = C3 ma low-level output v oh1 p00-p07, p20-p27, p30-p37, 4.5 v v dd 5.5 v, 1.0 v voltage p40-p47, p50-p57, p60-p67, i ol = 1 ma p70-p77, p100-p102, 3.5 v v dd < 4.5 v, 0.5 v p120-p124, p130-p137, i ol = 100 m a v ol2 eo0, eo1 v dd = 4.5 to 5.5 v, 1.0 v i ol = 3 ma high-level input i lih p00-p07, p10-p17, v i = v dd 3 m a leakage current p20-p24, p30-p37, p40-p47, p50-p57, p60-p67, p70-p77, p100-p102, p120-p124, reset remark unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
28 data sheet u12920ej1v0ds00 m pd178f098 parameter symbol conditions min. typ. max. unit low-level input i lil p00-p07, p10-p17, v i = 0 v C3 m a leakage current p20-p27, p30-p37, p40-p47, p50-p57, p60-p67, p70-p77, p100-p102, p120-p124, reset i loh1 p130-p137 v o = 15 v C3 m a i lol1 p130-p137 v o = 0 v 3 m a i loh2 p25-p27 v o = v dd C3 m a (at n-ch open drain i/o) i lol2 p25-p27 v o = 0 v 3 m a (at n-ch open drain i/o) i loh3 eo0, eo1 v o = v dd C3 m a i lol3 eo0, eo1 v o = 0 v 3 m a supply current note i dd1 fx = 4.5 mhz 5.0 18 ma i dd2 fx = 6.3 mhz 7.0 20 ma i dd3 fx = 4.5 mhz 0.3 0.8 ma i dd4 fx = 6.3 mhz 0.4 1.0 ma v ddr1 when crystal resonator is oscillating 3.5 5.5 v v ddr2 when crystal oscillation is power-failure detection 2.2 v stopped function v ddr3 data memory retained 2.0 v data retention i ddr1 when crystal oscillation is t a = 25 c, 2.0 4.0 m a current stopped v dd = 5 v i ddr2 2.0 20 m a dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) note excluding av dd current and v dd pll current. remarks 1. f x : system clock oscillation frequency 2. unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. output off leakage current data retention voltage when cpu is operating and pll is stopped. sine wave input to x1 pin v i = v dd in halt mode with pll stopped. sine wave input to x1 pin v i = v dd
29 data sheet u12920ej1v0ds00 m pd178f098 reference characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current i dd5 when cpu and pll are operating. 8 ma sine wave input to vcoh pin at f in = 160 mhz, v in = 0.15 v p-p ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit t cy at f x = 6.3 mhz 0.32 5.08 m s at f x = 4.5 mhz note 1 0.44 7.11 m s ti00, ti01 input t tih0 , 4/fsam note 2 s high-/low-level t til0 widths ti50, ti51 input f ti5 2 mhz frequency ti50, ti51 input t tih5 , 200 ns high-/low-level t til5 widths interrupt input t inth , intp0-intp7 1 m s high-/low-level t intl widths reset pin t rsl 10 m s low-level width notes 1. only when products not using iebus are supported. 2. f sam = f x /2, f x /4, f x /64 selectable by bits 0 and 1 (prm00 and prm01) of the prescaler mode register 0 (prm0). however, f sam = f x /8 when the valid edge of ti00 is selected as the count clock. cycle time (minimum instruction execution time)
30 data sheet u12920ej1v0ds00 m pd178f098 (2) serial interface (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns t kl1 t kcy1 /2 C 100 ns si0 setup time (to sck0 )t sik1 v dd = 4.5 to 5.5 v 100 ns 150 ns si0 hold time (from sck0 )t ksi1 400 ns so0 output delay time from sck0 ? t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck0 and so0 output line. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level width t kh2 ,v dd = 4.5 to 5.5 v 400 ns t kl2 800 ns si0 setup time (to sck0 )t sik2 100 ns si0 hold time (from sck0 )t ksi2 400 ns so0 output delay time from sck0 ? t kso2 c = 100 pf note 300 ns sck0 at rising or falling edge time t r2 , t f2 1000 ns note c is the load capacitance of so0 output line.
31 data sheet u12920ej1v0ds00 m pd178f098 (iii) sbi mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level width t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2 C 50 ns t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time (to sck0 )t sik3 v dd = 4.5 to 5.5 v 100 ns 300 ns sb0, sb1 hold time (from sck0 ) t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1 k w v dd = 4.5 to 5.5 v 0 250 ns sck0 ? c = 100 pf note 0 1000 ns sb0, sb1 ? from sck0 t ksb t kcy3 ns sck0 ? from sb0, sb1 ? t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of sck0, sb0 and sb1 output line. (iv) sbi mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level width t kh4 ,v dd = 4.5 to 5.5 v 400 ns t kl4 1600 ns sb0, sb1 setup time (to sck0 )t sik4 v dd = 4.5 to 5.5 v 100 ns 300 ns sb0, sb1 hold time (from sck0 ) t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1 k w v dd = 4.5 to 5.5 v 0 250 ns sck0 ? c = 100 pf note 0 1000 ns sb0, sb1 ? from sck0 t ksb t kcy4 ns sck0 ? from sb0, sb1 ? t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 at rising or falling edge time t r4 , t f4 1000 ns note r and c are the load resistance and load capacitance of sb0 and sb1 output line.
32 data sheet u12920ej1v0ds00 m pd178f098 (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w 1600 ns sck0 high-level width t kh5 c = 100 pf note t kcy5 /2 C 160 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time (to sck0 )t sik5 v dd = 4.5 to 5.5 v 300 ns 350 ns sb0, sb1 hold time (from sck0 ) t ksi5 600 ns sb0, sb1 output delay time from t kso5 0 300 ns sck0 ? note r and c are the load resistance and load capacitance of sck0, sb0 and sb1 output line. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 1600 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (to sck0 )t sik6 100 ns sb0, sb1 hold time (from sck0 ) t ksi6 t kcy6 /2 ns sb0, sb1 output delay time from t kso6 r = 1 k w v dd = 4.5 to 5.5 v 0 300 ns sck0 ? c = 100 pf note 0 500 ns sck0 at rising or falling edge time t r6 , t f6 1000 ns note r and c are the load resistance and load capacitance of sb0 and sb1 output line.
33 data sheet u12920ej1v0ds00 m pd178f098 parameter symbol test conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k w 10 m s scl high-level width t kh7 c = 100 pf note t kcy7 C 160 ns scl low-level width t kl7 t kcy7 C 50 ns sda0, sda1 setup time (to scl ) t sik7 200 ns sda0, sda1 hold time t ksi7 0ns (from scl ? ) sda0, sda1 output delay time t kso7 v dd = 4.5 to 5.5 v 0 300 ns (from scl ? ) 0 500 ns sda0, sda1 ? from scl or t ksb 200 ns sda0, sda1 from scl scl ? from sda0, sda1 ? t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns (vii) i 2 c bus mode (scl ... internal clock output) note r and c are the load resistance and load capacitance of scl, sda0 and sda1 output line. (viii) i 2 c bus mode (scl ... external clock input) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy8 1000 ns scl high-/low-level width t kh8, t kl8 400 ns sda0, sda1 setup time (to scl ) t sik8 200 ns sda0, sda1 hold time t ksi8 0ns (from scl ? ) sda0, sda1 output delay time t kso8 r = 1 k w v dd = 4.5 to 5.5 v 0 300 ns from scl ? c = 100 pf note 0 500 ns sda0, sda1 ? from scl or t ksb 200 ns sda0, sda1 from scl scl ? from sda0, sda1 ? t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns scl at rising or falling edge time t r8 , t f8 1000 ns note r and c are the load resistance and load capacitance of sda0 and sda1 output line.
34 data sheet u12920ej1v0ds00 m pd178f098 note c is the load capacitance of sck1 and so1 output line. (ii) 3-wire serial i/o mode (sck1 ... external clock input) (b) serial interface 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 800 ns sck1 high/low-level width t kh9 , t kcy9 /2 C 50 ns t kl9 si1 setup time (to sck1 )t sik9 100 ns si1 hold time (from sck1 )t ksi9 400 ns so1 output delay time (from sck1 ?) t kso9 c = 100 pf note 300 ns parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 800 ns sck1 high/low-level width t kh10 , 400 ns t kl10 si1 setup time (to sck1 )t sik10 100 ns si1 hold time (from sck1 )t ksi10 400 ns so1 output delay time (from sck1 ? )t kso10 c = 100 pf note 300 ns sck1 at rising or falling edge time t r10 , t f10 1000 ns note c is the load capacitance of so1 output line.
35 data sheet u12920ej1v0ds00 m pd178f098 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy11 800 ns sck1 high/low-level width t kh11 , t kcy11 /2 C 50 ns t kl11 si1 setup time (to sck1 )t sik11 100 ns si1 hold time (from sck1 )t ksi11 400 ns so1 output delay time (from sck1 ? )t kso11 c = 100 pf note 300 ns stb from sck1 t sbd t kcy11 /2 C 100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw t kcy11 /2 C 30 t kcy11 /2 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 100 ns (from busy signal detection timing) sck1 ? from busy inactive t sps 200 ns note c is the load capacitance of so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy12 800 ns sck1 high/low-level width t kh12 , 400 ns t kl12 si1 setup time (to sck1 )t sik12 100 ns si1 hold time (from sck1 )t ksi12 400 ns so1 output delay time (from sck1 ? )t kso12 c = 100 pf note 300 ns sck1 at rising or falling edge time t r12 , t f12 1000 ns note c is the load capacitance of so1 output line.
36 data sheet u12920ej1v0ds00 m pd178f098 note c is the load capacitance of sck3 and so3 output line. (ii) 3-wire serial i/o mode (sck3 ... external clock input) (c) serial interface 3 (i) 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck3 cycle time t kcy13 800 ns sck3 high/low-level width t kh13 , t kcy13 /2 C 50 ns t kl13 si3 setup time (to sck3 )t sik13 100 ns si3 hold time (from sck3 )t ksi13 400 ns so3 output delay time (from sck3 ?) t kso13 c = 100 pf note 300 ns parameter symbol test conditions min. typ. max. unit sck3 cycle time t kcy14 800 ns sck3 high/low-level width t kh14 , 400 ns t kl14 si3 setup time (to sck3 )t sik14 100 ns si3 hold time (from sck3 )t ksi14 400 ns so3 output delay time (from sck3 ? )t kso14 c = 100 pf note 300 ns sck3 at rising or falling edge time t r14 , t f14 1000 ns note c is the load capacitance of so3 output line. (d) serial interface uart0 (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate 38400 bps
37 data sheet u12920ej1v0ds00 m pd178f098 ac timing test point (excluding x1 input) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ti timing t til0 t tih0 ti00, ti01 1/f ti5 t til5 t tih5 ti50,ti51 interrupt input timing t intl t inth intp0 to intp7 reset input timing t rsl reset
38 data sheet u12920ej1v0ds00 m pd178f098 serial transfer timing 3-wire serial i/o mode: t kcym t klm t khm sck0, sck1, sck3 si0, si1, si3 so0, so1, so3 t sikm t ksim t ksom input data output data t rn t fn remark m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 sbi mode (bus release signal transfer): t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4
39 data sheet u12920ej1v0ds00 m pd178f098 sbi mode (command signal transfer): t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 2-wire serial i/o mode: t kso5, 6 t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t f6 t r6 i 2 c bus mode: scl sda0, sda1 t sbh t kl7, 8 t sbk t f8 t r8 t kcy7, 8 t ksi7, 8 t kh7, 8 t sik7, 8 t kso7, 8 t sbk t ksb t ksb
40 data sheet u12920ej1v0ds00 m pd178f098 3-wire serial i/o mode with automatic transmit/receive function: t sbw t sbd t kcy11 , 12 t kh11 , 12 t ksi11 , 12 t kso11 , 12 t sik11 , 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11 , 12 t f12 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh note the signal is not actually driven low here; it is shown as such to indicate the timing. iebus controller characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit iebus system f s fixed to mode 1 6.3 note mhz clock frequency note although the system clock frequency is 6.0 mhz in the iebus standard, in these products, normal operation is guaranteed at 6.3 mhz. remark 6.0 mhz and 6.3 mhz cannot both be used as the iebus system clock frequency.
41 data sheet u12920ej1v0ds00 m pd178f098 operating frequency a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit v dd = 4.5 to 5.5 v 1.0 %fsr 1.4 %fsr conversion time t conv 15.2 45.7 m s analog input voltage v ian 0v dd v notes 1. excluding quantization error ( 0.2%fsr) 2. this value is indicated as a ratio to the full-scall value. pll characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit f in1 vcol pin, mf mode, sine wave input, v in = 0.15 v p-p 0.5 3.0 mhz f in2 vcol pin, hf mode, sine wave input, v in = 0.15 v p-p 10 40 mhz f in3 vcoh pin, vhf mode, sine wave input, v in = 0.15 v p-p 60 130 mhz f in4 vcoh pin, vhf mode, sine wave input, v in = 0.3 v p-p 40 160 mhz remark the above values are the result of necs evaluation of the device. if the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values. ifc characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating f in5 amifc pin, amif count mode, sine wave input, 0.4 0.5 mhz frequency v in = 0.15 v p-p f in6 fmifc pin, fmif count mode, sine wave input, 10 11 mhz v in = 0.15 v p-p f in7 fmifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p remark the above values are the result of necs evaluation of the device. if the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values. total conversion error notes 1, 2
42 data sheet u12920ej1v0ds00 m pd178f098 flash memory programming characteristics (v dd = 3.5 to 5.5 v, t a = 10 to 40 c) (1) write/delete characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note t ddw when v pp = v pp1 , f x = 6.3 mhz 23 ma write current (v pp pin) note i ppw when v pp = v pp1 , f x = 6.3 mhz 20 ma delete current (v dd pin) note i dde when v pp = v pp1 , f x = 6.3 mhz 23 ma delete current (v pp pin) note i ppe when v pp = v pp1 100 ma unit delete time t er 0.5 1 1 s total delete time t era 20 s number of overwrite c wrt delete and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 at flash memory programming 9.7 10.0 10.3 v note av dd current and port current (current flowing to internal pull-up resistor) are not included. remark f x : system clock oscillation frequency (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 m s v pp setup time from v dd t drpsr v pp high voltage 1.0 m s reset setup time from v pp t psrrf v pp high voltage 1.0 m s v pp count start time from reset t rfcf 1.0 m s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 m s v pp counter low-level width t cl 8.0 m s v pp counter noise elimination width t nfw 40 ns
43 data sheet u12920ej1v0ds00 m pd178f098 flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count
44 data sheet u12920ej1v0ds00 m pd178f098 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 ? 5 s 3.0 max. m 0.15 + 0.10 - 0.05 c d a b s 8. package drawing
45 data sheet u12920ej1v0ds00 m pd178f098 9. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. table 9-1. soldering conditions for surface-mount type m pd178f098gf-3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec max. (210 c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 sec max. (200 c min.), vp15-00-3 number of times: 3 max. wave soldering solder bath temperature: 260 c max., time: 10 sec max., ws60-00-1 number of times: 1, preheating temperature: 120 c max., (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec max (per device side) C caution do not use two or more soldering methods in combination (except partial heating).
46 data sheet u12920ej1v0ds00 m pd178f098 appendix a. development tools the following development tools are available for development of systems using the m pd178078 and 178098 subseries. language processor software ra78k/0 notes 1, 2, 3 assembler package common to 78k/0 series cc78k/0 notes 1, 2, 3 c compiler package common to 78k/0 series df178098 notes 1, 2, 3 device file for m pd178078 subseries and m pd178098 subseries cc78k0-l notes 1, 2, 3 c compiler library source file common to 78k/0 series flash memory writing tools fashpro iii dedicated flash programmer (part number: fl-pr3 note 4 , pg-fl3) fa-100gf-3ba note 4 flash programmer adapter debugging tools ? when in-circuit emulator ie-78k0-ns is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board for enhancing and expanding the ie-78k0-ns function ie-70000-98-if-c interface adapter necessary when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable necessary when a notebook-type pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter necessary when a ibm pc/at tm compatible machine is used as host machine (isa bus supported) ie-70000-pci-if interface adapter necessary when a pc with a pci bus is used as host machine ie-178098-ns-em1 emulation board to emulate m pd178078 and 178098 subseries np-100gf note 4 emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (gf-3ba type) sm78k0 notes 1, 2 system simulator common to 78k/0 series id78k0-ns notes 1, 2 integrated debugger common to 78k/0 series df178098 notes 1, 2, 3 device file for m pd178078 subseries and m pd178098 subseries notes 1. pc-9800 series (japanese windows tm ) based 2. ibm pc/at compatible machine (japanese/english windows) based 3. hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm (sunos tm , solaris tm ) based, news tm (news-os tm ) based 4. products of naito densei machida mfg. co., ltd. (tel: 044-822-3813). remark use the ra78k0, cc78k0, and sm78k0 in combination with the df178098.
47 data sheet u12920ej1v0ds00 m pd178f098 when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter necessary when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter necessary when ibm pc/at compatible machine is used as host machine (isa bus supported) ie-70000-pci-if interface adapter necessary when a pc with a pci bus is used as host machine ie-78000-r-sv3 interface adapter and cable necessary when ews is used as host machine ie-178098-ns-em1 emulation board to emulate m pd178078 and 178098 subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-178098-ns-em1 on ie-78001-r-a ep-78064gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (gf-3ba type) sm78k0 notes 1, 2 system simulator common to 78k/0 series id78k0 notes 1, 2 integrated debugger common to 78k/0 series df178098 notes 1, 2, 3 device file for m pd178078 subseries and m pd178098 subseries real-time os rx78k/0 notes 1, 2, 3 real-time os for 78k/0 series mx78k0 notes 1, 2, 3 os for 78k/0 series notes 1. pc-9800 series (japanese windows) based 2. ibm pc/at compatible machine (japanese/english windows) based 3. hp9000 series 700 (hp-ux) based, sparcstation (sunos, solaris) based, news (news-os) based remark use the sm78k0 in combination with the df178098.
48 data sheet u12920ej1v0ds00 m pd178f098 device documents title document no. japanese english m pd178076, 178078, 178096, 178098 data sheet u12885j u12885e m pd178f098 data sheet u12920j this document m pd178078, 178098 subseries users manual u12790j u12790e 78k/0 series users manual - instruction u12326j u12326e 78k/0 series application note basics (i) u12704j u12704e 78k/0, 78k/0s series flash memory write application note u14458j u14458e development tool documents (users manual) title document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly u11789j u11789e language cc78k0 c compiler operation u11517j u11517e language u11518j u11518e ie-78001-r-a u14142j to be prepared ie-78k0-ns u13731j u13731e ie-178098-ns-em1 u14013j u14013e ep-78064 eeu-934 eeu-1469 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator u10092j u10092e id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e id78k0-ns integrated debugger windows based reference u12900j u12900e operation u14379j to be prepared appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. external parts user open interface specifications caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
49 data sheet u12920ej1v0ds00 m pd178f098 title document no. japanese english 78k/0 series real-time os fundamental u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 fundamental u12257j u12257e other documents title document no. japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality guides on nec semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality/reliability handbook c12769j microcomputer product series guide u11416j related documents for embedded software (users manual) caution the contents of the above documents are subject to change without notice. ensure that the latest versions are used in design work, etc.
50 data sheet u12920ej1v0ds00 m pd178f098 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. iebus is a trademark of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
51 data sheet u12920ej1v0ds00 m pd178f098 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd178f098 m8e 00. 4 the information in this document is current as of june, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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